XCR3128XL-10VQ100I

Product Summary

The XCR3128XL-10VQ100I is a 3.3V 128 macrocell, CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of eight function blocks provide 3,000 usable gates. Pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 145 MHz.

Parametrics

XCR3128XL-10VQ100I absolute maximum ratings: (1)VOH(2) Output High voltage IOH = –8 mA, 2.4 V min; (2)VOL Output Low voltage for 3.3V outputs IOL = 8 mA, 0.4 V max; (3)IIL Input leakage current VIN = GND or VCC: –10 μA min 10 μA max; (4)IIH I/O High-Z leakage current VIN = GND or VCC: –10 μA min 10 μA max; (5)ICCSB Standby current VCC = 3.6V : 100 μA max; (6)ICC Dynamic current(3,4) f = 1 MHz: 1 mA; f = 50 MHz: 30mA; (7)CIN Input pin capacitance(5) f = 1 MHz: 8 pF; (8)CCLK Clock input capacitance(5) f = 1 MHz: 12 pF; (9)CI/O I/O pin capacitance(5) f = 1 MHz: 10 pF.

Features

XCR3128XL-10VQ100I features: (1)Lowest power 128 macrocell CPLD; (2)6.0 ns pin-to-pin logic delays; (3)System frequencies up to 145 MHz; (4)128 macrocells with 3,000 usable gates; (5)Available in small footprint packages: 144-pin TQFP (108 user I/O pins); 144-ball CS BGA (108 user I/O); 100-pin VQFP (84 user I/O); (6)Optimized for 3.3V systems: Ultra low power operation; 5V tolerant I/O pins with 3.3V core supply; Advanced 0.35 micron five layer metal EEPROM process; Fast Zero Power(FZP) CMOS design technology; (7)Advanced system features: In-system programming; Input registers; Predictable timing model; Up to 23 available clocks per function block; Excellent pin retention during design changes; Full IEEE Standard 1149.1 boundary-scan (JTAG); Four global clocks; Eight product term control terms per function block; (8)Fast ISP programming times; (9)Port Enable pin for additional I/O; (10)2.7V to 3.6V supply voltage at industrial temperature range; (11)Programmable slew rate control per output; (12)Security bit prevents unauthorized access; (13)Refer to XPLA3 family data sheet (DS012) for architecture description.

Diagrams